Extended SPARC ISA

Added line is this color

Deleted line is this color

 
-<p>F S "D" E M W</p>
+<p>F "S" D E M W</p>
 <p> </p>
 <p>I-Cache line=16 inst</p>
 <p> </p>
 <p>Checkpoint: sethi 0x3, %g0</p>
 <p>Delay slots: 3=&gt; to ensure state checkpointed when instructions in E, M,
 W clear</p>
 <p> </p>
 <p>Commit: sethi 0x2, %g0</p>
 <p>Delay slots: 0</p>
 <p> </p>
 <p>Rollback:</p>
-<p>stx %g0, [%g0]</p>
-<p>rbk</p>
+<p>sethi 0x1, %g0</p>
+<p>rbk (branch always)</p>
+<p>nop</p>
 <p> </p>
-<p>stx %g0, %g0 = 0xC070 0000</p>
 <p>Branch Always</p>
 <p>rbk = 0x30BF FFFF =&gt; branch to stx in pc-4</p>
 <p>BA = 0x1080 0000</p>
 <p>Offset bits = 0x3F FFFF</p>
-<p>Annull bit = 0x2000 0000</p>
+<p>*Annull bit = 0x2000 0000</p>
 <p> </p>
 <p> </p>
 <p>OBSOLETE</p>
 <p>Rollback: sethi 0x1, %g0</p>
 <p>Delay slots:3</p>
 <p>=&gt; pc modified when rbk is in E, so F, S, D have to be clear</p>
 <p>=&gt;*NOTE:rbk asseted in W so that processor state for inst before rbk are
 not affected</p>
 <p> </p>
 <p>OBSOLETE</p>
 <p>New instructions</p>
 <p>op=0x2 (arith inst), op3=0x36, opf[8:4]=0x10</p>
 <p><u>Checkpoint</u></p>
 <p><strong>CHK<br></strong></p>
 <p>opf[1:0] = 0x3</p>
 <p>opcode=0x81b02060</p>
 <p> </p>
 <p><u>Rollback</u></p>
 <p><strong>RBK</strong></p>
 <p>opf[1:0] = 0x1</p>
 <p>Notes: Two subsequent instructions after RBK have to be NOPs. We plan to
 include architecture support to flush the Fetch and Schedule stage at a later
 point.</p>
 <p> opcode=0x81b02020</p>
 <p> </p>
 <p><u>Commit</u></p>
 <p><strong>CMT</strong></p>
 <p>opf[1:0] = 0x2</p>
 <p> Notes: A forced commit could also occur as a result of an exception at the
 maximun checkpoint lenght that is supported by the transactional memory
 design.</p>
 <p>opcode=0x81b02040</p>
 <p> </p>
 <hr width="100%" size="2">
 <p> </p>