Welcome

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 <p>Welcome to the project page of OpenSPARC Checkpoint project.</p>
 <p>Our goal is to add checkpoint creation and maintainance into the OpenSPARC
 architecture. A checkpoint includes architecture and memory state. Supported
 post checkpoint operations include rollback and commit.</p>
 <p> </p>
 <p>At this point the project is targetting to synthesize a single core, single
 thread OpenSPARC T1 processor on a Xilinx Virtex 4 FPGA.</p>
 <p> </p>
-<p>Please visit the<a href=
-"http://sparccheckpoint.atwiki.com/page/About%20Us">About Us</a>page for more
+<p>Please visit the <a href=
+"http://sparccheckpoint.atwiki.com/page/About%20Us">About Us</a> page for more
 information about the team.</p>
 <p> </p>
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