Extended SPARC ISA

F "S" D E M W

I-Cache line=16 inst

Checkpoint: sethi 0x3, %g0

Delay slots: 3=> to ensure state checkpointed when instructions in E, M, W clear

Commit: sethi 0x2, %g0

Delay slots: 0

Rollback:

sethi 0x1, %g0

rbk (branch always)

nop

Branch Always

rbk = 0x30BF FFFF => branch to stx in pc-4

BA = 0x1080 0000

Offset bits = 0x3F FFFF

*Annull bit = 0x2000 0000

OBSOLETE

Rollback: sethi 0x1, %g0

Delay slots:3

=> pc modified when rbk is in E, so F, S, D have to be clear

=>*NOTE:rbk asseted in W so that processor state for inst before rbk are not affected

OBSOLETE

New instructions

op=0x2 (arith inst), op3=0x36, opf[8:4]=0x10

Checkpoint

CHK

opf[1:0] = 0x3

opcode=0x81b02060

Rollback

RBK

opf[1:0] = 0x1

Notes: Two subsequent instructions after RBK have to be NOPs. We plan to include architecture support to flush the Fetch and Schedule stage at a later point.

 opcode=0x81b02020

Commit

CMT

opf[1:0] = 0x2

 Notes: A forced commit could also occur as a result of an exception at the maximun checkpoint lenght that is supported by the transactional memory design.

opcode=0x81b02040