Welcome

Welcome to the project page of OpenSPARC Checkpoint project.

Our goal is to add checkpoint creation and maintainance into the OpenSPARC architecture. A checkpoint includes architecture and memory state. Supported post checkpoint operations include rollback and commit.

At this point the project is targetting to synthesize a single core, single thread OpenSPARC T1 processor on a Xilinx Virtex 4 FPGA.

Please visit the About Us page for more information about the team.